Performance pathologies in hardware transactional memory
نویسندگان
چکیده
منابع مشابه
Hardware-Supported Transactional Memory
In this report, we describe a number of Hardware Transactional Memory (HTM) designs and their basic mechanisms used for better programmability and higher performance than conventional synchronization techniques based on locking. We compare the systems considering their programming model, hardware design challenges, transactional dataset constraints and forward progress guarantees. As high-speed...
متن کاملImproving Performance by Reducing Aborts in Hardware Transactional Memory
The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, and may lead to aborts that increase wasted work, and degrade performance. A promising approach to reducing conflicts at runtime is dynamically, and transparently, reordering the execution of transactions upon discovery ...
متن کاملUsing A Runtime to Overcome The Pathologies in Hardware Transactional Memory Systems
As one of the most potential solution to improve thread level parallelism and reduce most ordinary programmers’ burden on parallel programming, transactional memory (TM) systems have attracted a great deal of attention from both industry and academic since the notion was proposed in 1993. Since then, various designs and implementations are proposed to improve the performance while reducing the ...
متن کاملPerformance Modelling of Intel’s Hardware Transactional Memory Implementation
Transactional Memory (TM) is a recent alternative to traditional lock based synchronization mechanisms for parallel programming. This report analyses the state of the art in the area of performance modelling for transactional memory systems, as well as for concurrency control mechanisms for database management systems. My analysis of existing literature in these areas highlights the existence o...
متن کاملExploiting object structure in hardware transactional memory
Transactional Memory (TM) is receiving attention as a way of expressing parallelism for programming multi-core systems. As a parallel programming model it is able to avoid the complexity of conventional locking. TM can enable multi-core hardware that dispenses with conventional bus-based cache coherence, resulting in simpler and more extensible systems. This is increasingly important as we move...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: ACM SIGARCH Computer Architecture News
سال: 2007
ISSN: 0163-5964
DOI: 10.1145/1273440.1250674